基于FPGA的感应机和电力电子测试系统

OPAL-RT

An Induction Machine and Power Electronic Test System on FPGA
! x+ d3 ^' n5 t) a! D2 y% y基于FPGA的感应机和电力电子测试系统
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7 r; o) W0 u5 N8 R; lAbstract
: Q  G, G, F& c) O1 z7 R& m% NThis paper presents an FPGA test system composed of an Induction Machine (IM), configurable as a Doubly-Fed Induction Machine (DFIM) or squirrel-cage induction machine, along with power electronic models suitable for virtual motor drive control development. The IM model is designed so that all parameters can be modified online. The power electronic part is customizable using a variable topology FPGA solver called Electric Hardware Solver (eHS). The system is designed for fast design iteration process by allowing circuit and parameter modification with a unique bitstream. The system allows control engineers to validate production controllers in real-time using a virtual IM.
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这篇文章介绍的FPGA测试系统包含一套可被配置为双馈感应机（Doubly-Fed Induction Machine）或鼠笼型感应机（squirrel-cage induction machine）的感应机，以及针对虚拟电机驱动控制开发的电力电子模型。该感应机模型可实现所有参数在线修正。电力电子部分通过使用一种叫做电子硬件解算器（Electric Hardware Solver：eHS）的可变式拓扑FPGA解算器达到可自定义功能。该系统利用特殊的比特流修改电路和参数实现快速迭代过程。这套系统让控制工程师利用虚拟感应机实现实时生产控制器验收.

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