关于Signal Generator模块
做一个仿真发现这个信号发生器所能设定的最大频率为1000HZ，即使设定的频率再大输出仍然是1000HZ，且频率越大时，波形失真越厉害如图，图中设定频率为5000HZ，结果图形显示为1000HZ，当设定频率为小于等于1000HZ的频率，波形显示正常。当大于一定的频率之后，如50HZ，则波形失真很小，为正规的方波。 窃以为，如果波形发生器频率有上限限制，应该在该模块的说明里注释一下，不过偶没有找到，觉得有点奇怪，大家有什么想法？ 仿真步长是多少？ 3# suner1986
试过50us和5us 没区别 1# fallingstar64
难道大家都没发现这个问题吗？？？？
还是我哪里设置不对，大家可以拿它做下实验 确实有问题，刚试了一下，的确像楼主所说的，不太对。 这个装置好像不能输出超过1000Hz的波形，可能是它的极限了，呵呵。 仿真步长和plot步长要协调一下。。
不是元件有问题 是plot时时间窗口过大 所以就遗漏了中间的量
但因为是周期信号 所以输出的还是周期信号。。
你把plot和仿真的step设置一样 且要小于你的设置周期试试。。 8# stoon123
弄好了，多谢版主~~~~~ 本帖最后由 fallingstar64 于 2009-8-11 16:21 编辑
弄好了，多谢版主~
贴一个版主说的英文帮助，看来要好好学习了~~~~
Channel Plot Step (us)
This is the time interval at which EMTDC sends data to PSCAD for plotting as well as writing data to Output Files.It is always a multiple of the EMTDC simulation time step.Usually a 250 ms plot step provides a reasonable resolution and speed.
Lower sampling intervals (higher sampling rate) can considerably slow down the simulation speed due to an excessive transfer of data from EMTDC to PSCAD (without adding much to the plot resolution).Users can experiment with this number for a given Project.If the sampling interval is too large, the waveforms may appear 'choppy'.If you are debugging the case, it is a good practice to plot every point in the simulation, that is, plot sampling time as equal to EMTDC simulation time step.
A trap that even the most experienced engineers can readily fall into is the setting of plot step too broad with respect to the level and period of noise in the signal.If a signal is periodic at a frequency similar to the plot step interval, the perceived output may be quite different to the actual signal.As a basic rule:If you are puzzled by the results observed from a plotted simulation output, run the case with the plot step equal to the EMTDC time step and compare the results.
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